Semiconductor devices having a capacitor array in which a plurality of unit capacitor cells are arranged on a semiconductor substrate have been known to those skilled in the art. Such a capacitor array may be used for a D/A converter, a switched capacitor, etc.
FIG. 39 is a circuit diagram showing part of a D/A converter circuit in which a related-art capacitor array is utilized. Condensers C0 through Cn are connected in parallel. Voltages V0 through Vn corresponding to the respective condensers C0 through Cn are applied from an input side to respective lower electrodes CL in a binary fashion. On the output side, upper electrodes CU of the respective condensers C0 through Cn are connected together to output an analog signal. The input side is low impedance, and the output side is high impedance.
FIG. 40 is a drawing illustrating an example of a plane arrangement of a semiconductor device 200 having a related-art capacitor array 150 for implementing the circuit shown in FIG. 39. In FIG. 40, 9 capacitor cells C0 through C8 each serving as a unit capacitance are arranged in a 3-by-3 matrix form, thereby constituting the capacitor array 150 as a whole. Each capacitor cell has a lower electrode CL and an upper electrode CU facing each other. The area size of the upper electrode CU is smaller than the area size of the lower electrode CL. The lower electrodes CL of the respective capacitor cells C0 through C8 are coupled to input interconnects V0 through V8, respectively. Input signals are supplied to the respective capacitor cells C0 through C9 via the input interconnects V0 through V8, respectively. Signal components of the input signals are converted into an analog converted signal by coupling the input nodes to a predetermined reference to redistribute electric charges after the charging of the unit capacitor cells C0 through C8.
The capacitor cells C0 through C3 and C5 through C8 are arranged at the perimeter of the capacitor array 150. Accordingly, the input interconnects V0 through V3 and V5 through V8 can directly be coupled to the respective lower electrodes CL at the outside edge from outside the capacitor array 150. With this arrangement, the applied input signals do not significantly affect the other capacitor cells.
Patent Document 1, for example, discloses a capacitor array comprised of four unit-capacitor cells in which shield lines are disposed on both sides of the upper electrode interconnect line such as to suppress capacitive couplings between the upper electrode interconnect line and lower electrode interconnect lines as well as between the upper electrode interconnect line and the lower electrodes.    [Patent Document 1] Japanese Patent Application Publication No. 2003-17575